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Transfer clash-cores tests in clash-testsuite to clash-cores #3

Merged
merged 39 commits into from
Aug 26, 2024
Merged

Transfer clash-cores tests in clash-testsuite to clash-cores #3

merged 39 commits into from
Aug 26, 2024

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t-wallet
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@t-wallet t-wallet commented Aug 26, 2024 •
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Repeat this PR

git remote add temp git@github.com:clash-lang/clash-compiler
git fetch temp
# The hash refers to the commit before "remove clash-cores from clash-testsuite".
git branch temp_branch 280905d3f9754ee9656522d593fed33005f56263
git checkout temp_branch

git subtree split --prefix=tests/shouldfail/Cores -b shouldfail-cores
git subtree split --prefix=tests/shouldwork/Cores -b shouldwork-cores

git checkout transfer-clash-testsuite

git subtree add --prefix=tests/shouldfail/Cores shouldfail-cores
git subtree add --prefix=tests/shouldwork/Cores shouldwork-cores

# Move the tests to their correct location
git mv tests/shouldfail/Cores/* tests/shouldfail/
git mv tests/shouldwork/Cores/* tests/shouldwork/
rmdir tests/shouldfail/Cores
rmdir tests/shouldwork/Cores
git mv tests/* test/
rmdir tests

# Cleanup
git branch -d shouldfail-cores
git branch -d shouldwork-cores
git branch -d temp_branch
git remote remove temp

DigitalBrains1 and others added 30 commits July 6, 2021 15:37
@DigitalBrains1
clash-cores New: Xilinx float addition (#1869)
baa1214 
Single-precision floating point addition, realized through instantiation
of the Xilinx Floating-Point LogiCORE IP v7.1.
@DigitalBrains1
clash-cores New: Xilinx float sub, mul and div
1fdf4a3 
Single-precision floating point operations, realized through
instantiation of the Xilinx Floating-Point LogiCORE IP v7.1.
@DigitalBrains1
Xilinx.Floating tests: Use MemBlob
d27d578 
Also don't use `MagicHash` since it's not enabled by default for
`clash-testsuite`.
@DigitalBrains1
New: Xilinx.Floating.fromU32
b544e84 
New in `clash-cores`: convert `Unsigned 32` to `Float` with Xilinx IP.
@vmchale @martijnbastiaan @DigitalBrains1
Add Xilinx dual clock FIFO to clash-cores (#2270)
ef7b125 
Only a limited number of configurations is supported; see module
documentation.

The Haskell model does not correspond exactly to RTL.

This closes bittide/bittide-hardware#59

Co-authored-by: Martijn Bastiaan <martijn@hmbastiaan.nl>
Co-authored-by: Peter Lebbing <peter@digitalbrains.com>
@martijnbastiaan
New: Xilinx.Floating.fromS32 (#2343)
d10f458 
New in `clash-cores`: convert `Signed 32` to `Float` with Xilinx IP.
@martijnbastiaan
New: Clash.Cores.Xilinx.Floating.compare
fe27718
@christiaanb
Add support for GHC 9.2 to clash-testsuite
e9c18b5
@DigitalBrains1
Test suite: multiple tests in one file
9442dbe 
PR #2345 made it possible to use multiple build targets in all tools.
This PR leverages that functionality, combining build targets that were
previously split over multiple top entity files.

Not counting Vivado, 90% of `clash-testsuite`'s execution time is spent
on Clash startup costs. These costs are shared between the multiple
build targets, making the test suite a bit quicker.
@kleinreact
Add Xilinx VIO IP Core
27e65ee
@kleinreact
Add Xilinx VIO IP Core
6609a67
@martijnbastiaan @DigitalBrains1
Add Xilinx tdpbram to clash-cores
fb2253e 
Co-authored-by: Peter Lebbing <peter@digitalbrains.com>
@martijnbastiaan
Add XPM_CDC_GRAY to clash-cores
c10a85b
@martijnbastiaan
Add XPM_CDC_SINGLE to clash-cores
27a27fe
@christiaanb
GHC 9.4 support for test Cores/Xilinx/DcFifo/Basic
c82b73a
@martijnbastiaan
Add XPM_CDC_ARRAY_SINGLE to clash-cores (#2459)
05f542f
@hiddemoll @martijnbastiaan
Add loading of HDL to VIO tests
8348fcf 
Before adding the `KEEP` attribute to `vioProbe` ports, clash did
not generate valid VHDL since the types of vioProbe declaration
and instantiation did not match. This has been fixed, but to make
sure these bugs do not occur again the circuits in `shouldwork`
are now loaded in Vivado.

The circuits in `shouldwork` also did not produce valid VHDL, as
the words `in` and `out` are reserved. The names of ports have
been updated to produce valid VHDL.
@martijnbastiaan @hiddemoll
Add custom naming to VIO probes (#2483)
fcacc02 
A design with VIO probes is inspected (through the GUI of the
synthesis tool) when programmed on an FPGA. It therefore makes sense
to give each individual probe a logical name.

The names of in- and output ports should be given as two `Vec`tor of
`Strings`, where the length should match the number of probes.

Co-authored-by: Hidde Moll <hidde@qbaylogic.com>
@martijnbastiaan @hiddemoll
Add custom naming to VIO probes (#2483)
28f6649 
A design with VIO probes is inspected (through the GUI of the
synthesis tool) when programmed on an FPGA. It therefore makes sense
to give each individual probe a logical name.

The names of in- and output ports should be given as two `Vec`tor of
`Strings`, where the length should match the number of probes.

Co-authored-by: Hidde Moll <hidde@qbaylogic.com>
@martijnbastiaan
Add XPM_CDC_HANDSHAKE to clash-cores
3b12f8e
@martijnbastiaan
Error on unreliable name generation in VIO blackbox
4a6a82a 
Fixes #2497
@martijnbastiaan
Account for setName and friends in vioProbe (#2524)
e57c91e 
Fixes #2501
@martijnbastiaan
Use CLASH_OPAQUE through libraries
304af20
@martijnbastiaan
Add unsafe{From,To}Active{Low,High}
8c311de
@christiaanb
Allow zero-bit result for prim fun-args (#2550)
460c40d 
Fixes #2549
@martijnbastiaan
Add Clash.Cores.Xilinx.Ila
52eccc6
@martijnbastiaan @DigitalBrains1
Add noReset, andReset, and orReset
05c6bba 
Co-authored-by: Peter Lebbing <peter@digitalbrains.com>
@leonschoorl
clash-cores: Fix xpmCdcHandshake (#2610)
0ea8be3 
* The HDL generated incorrectly set DEST_EXT_HSK=0,
   configuring it to generate acks automatically.
   While the exposed API and simulation model assumed external handshaking.
 * The dstStages and srcStages settings were flipped.

This also updates the test so it can detect that first error.
And improves the haddock a bit to clarify what the settings do and relate them to the XPM documentation.
@martijnbastiaan
Combine function names when specializing
2123259 
Given a global binder `accum` and an application `f accum`, Clash
now calls the new, specialized binder `f_accum` instead of just
`accum`, provided that both are marked `NOINLINE`/`OPAQUE`. This
more accurately reflects the body of the function and will result
in more sensible file names. For example, previously Clash
would generate a separate file `accum.{v,vhdl}` that contained the
inlined bodies of both `f` and `accum`. After this patch, it will
generate `f_accum.{v,vhdl}`.

Tabulated the new behavior looks like:

| OPAQUE        | Old name for `f g` | New name for `f g` |
|---------------|--------------------|--------------------|
| `f`           | `g`                | `f`                |
| `g`           | `g`                | `g`                |
| `f` and `g`   | `g`                | `f_g`              |
| !`f` and !`g` | `g`                | `f_g`              |

Fixes #2508
@leonschoorl @martijnbastiaan
Clean up XpmCdc tests code
8d00c75
leonschoorl and others added 9 commits April 7, 2024 10:26
@leonschoorl @martijnbastiaan
Fix tests XpmCdcSingle, XpmCdcArraySingle, XpmCdcGray
faacebe 
XpmCdcSingle was using as iots test signal:
  fromList [0..] :: Signal dom (Unsigned 1)
which evaluates to 0 :> 1 :> errorX "finite list".
When that flows though sample . fmap pack . unsafeSynchronizer it turns
into
  [0b0, 0b1, 0b., 0b., 0b., ...

Now we use the random package to generate random test data.
And the seed is also randomly generated via TH on each compile.
So everytime you recompile you get different test data.
@martijnbastiaan
Add XPM_CDC_PULSE to clash-cores
fbef76a
@leonschoorl @martijnbastiaan
Add resets to xpmCdcPulseWith
868952f
@leonschoorl @martijnbastiaan
Add xpmCdcSyncRst
77080f4
@lmbollen @martijnbastiaan
Add Clash.Cores.Xilinx.Unisim.DnaPortE2
b6cc60d 
Co-authored-by: Martijn Bastiaan <martijn@hmbastiaan.nl>
@martijnbastiaan
Merge pull request #2509 from clash-lang/fix-2508
25b6699 
Combine function names when specializing
@t-wallet
Add 'tests/shouldfail/Cores/' from commit '4a6a82ab88b43de7e1b2639d3b…
6e65384 
…c42f0e5788589c'

git-subtree-dir: tests/shouldfail/Cores
git-subtree-mainline: e205083
git-subtree-split: 4a6a82a
@t-wallet
Add 'tests/shouldwork/Cores/' from commit '25b66996823e25f7538365f604…
f8e1a92 
…f30958fac33374'

git-subtree-dir: tests/shouldwork/Cores
git-subtree-mainline: 6e65384
git-subtree-split: 25b6699
@t-wallet
Move over relevant clash-testsuite tests
e1d612d
@t-wallet t-wallet changed the title Transfer clash-cores tests in clash-testsuite Transfer clash-cores tests in clash-testsuite to clash-cores Aug 26, 2024
@t-wallet t-wallet merged commit 2dee5a3 into main Aug 26, 2024
@t-wallet t-wallet deleted the transfer-clash-testsuite branch August 26, 2024 13:08
@t-wallet t-wallet mentioned this pull request Aug 26, 2024
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9 participants
@t-wallet @DigitalBrains1 @vmchale @martijnbastiaan @christiaanb @kleinreact @hiddemoll @leonschoorl @lmbollen