Superscalar dual-issue RISC-V processor
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Updated
Jul 31, 2024 - SystemVerilog
Superscalar dual-issue RISC-V processor
Implementación del procesador monociclo RISC-V en System Verilog.
This project template is designed to streamline the development of SystemVerilog projects using Verilator, GTKWave, and Make. The template includes a Makefile with various recipes for compiling, simulating, and visualizing the design. It also includes a directory structure for organizing the HDL files, test benches, and simulation waveforms.
This repository contains an extensive learning journey of SystemVerilog, exercises and projects to enhance the understanding and proficiency in the hardware description language
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