0xArt / RGMII_Ethernet_Transceiver_Verilog Star 21 Code Issues Pull requests Verilog module to transmit/receive to/from RGMII compatible ethernet PHY fpga verilog ethernet rgmii Updated Dec 31, 2022 Verilog
0xArt / Passe_Passe_Network_Switch Star 5 Code Issues Pull requests A FPGA layer 2 network switch with the unique ability of having virtual ports that can transmit and receive UDP data. fpga network udp switch ethernet rmii rgmii layer-2 Updated Jul 7, 2024 SystemVerilog
kokjo / misc_fpga Star 4 Code Issues Pull requests iCE40 and ECP5 fpga libraries and projects. Using the open source toolchain yosys+nextpnr. Quality may vary. fpga uart blinky yosys ice40 pmod ecp5 nextpnr rgmii Updated Jun 30, 2019 Verilog