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RISC-V support #2800

Merged
merged 5 commits into from
Oct 20, 2022
Merged

RISC-V support #2800

merged 5 commits into from
Oct 20, 2022

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tnayuki
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@tnayuki tnayuki commented Feb 20, 2022

Description

Add RISC-V support in compiler LLVM and universal & dylib engine.

Review

  • Add a short description of the change to the CHANGELOG.md file

Comment on lines +218 to +234
// TODO: totally non-portable way to change ABI
unsafe {
pub struct MyTargetMachine {
pub target_machine: *const u8,
}

let my_target_machine: MyTargetMachine = std::mem::transmute(llvm_target_machine);

*((my_target_machine.target_machine as *mut u8).offset(0x410) as *mut u64) = 5;
std::ptr::copy_nonoverlapping(
"lp64d\0".as_ptr(),
(my_target_machine.target_machine as *mut u8).offset(0x418),
6,
);

std::mem::transmute(my_target_machine)
}
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This will need to be in llvm-sys or inkwell, right?

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Yes, but LLVM C API to change ABI doesn't seem to exist, so it should also be added.

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Thanks for the context.
Do you think we can create an issue on the LLVM project and add an extra comment in this source with a reference to the URL that new LLVM issue?

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Sorry for the late reply as I have been busy with my day job😢
I checked LLVM again, and I found that it seems by this change the correct ABI will be specified in LLVM 15, so I will try it.
llvm/llvm-project@4e115b7

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I have compiled and tested that on a StarFive board running Fedora, and I have some test that are failling. Do you have tests failling also on your side?

@tnayuki
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tnayuki commented Mar 23, 2022

@ptitSeb Sorry for late response
Which tests failed on your board?

I have compiled and tested that on a StarFive board running Fedora, and I have some test that are failling. Do you have tests failling also on your side?

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tnayuki commented Mar 23, 2022

@ptitSeb on my HiFive Unmatched board,
deterministic::deterministic_empty, deterministic::deterministic_table, traps::test_trap_stack_overflow::llvm::universal and traps::test_trap_trace::llvm::universal were failed, but I have not properly investigated the cause.

By the way some tests that seem to use filesystem were ignored.

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ptitSeb commented Mar 23, 2022

@ptitSeb on my HiFive Unmatched board, deterministic::deterministic_empty, deterministic::deterministic_table, traps::test_trap_stack_overflow::llvm::universal and traps::test_trap_trace::llvm::universal were failed, but I have not properly investigated the cause.

By the way some tests that seem to use filesystem were ignored.

Yes, the traps one are also failing on my side. But I get a segfault on simd tests. The CPU doesn't have any SIMD extension, but I was assuming llvm should use non-simd path? Likewise, I haven't analysed yet.
I use a custom built LLVM-13.0.1, as the Fedora image of the VisionFive only have llvm-11 available.

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ptitSeb commented Mar 23, 2022

Also, wasmer source have evolved lately, with some new mecanism around trap and stack handling. You should try to update your fork.
Unfortunatly, the stack switcher corosensei is not compatible with Risc-V for now, so this will need to be added too (@Amanieu ), or find a way to have a generic fallback mecanism for unsupported platforms.

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@ptitSeb I think corosensei it is compatible with RISC-V?

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ptitSeb commented Mar 23, 2022

@ptitSeb I think corosensei it is compatible with RISC-V?

There is a riscv.rs source file yes, but it's not shown on the readme as a supported arch.

@syrusakbary syrusakbary added this to the v3.0 milestone Jun 1, 2022
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[Question]: I recently came across this and was just curious. Does this PR mean there will be Wasmer support for the likes of ESP32 MCUs? Thanks for any info.

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ptitSeb commented Jun 23, 2022

[Question]: I recently came across this and was just curious. Does this PR mean there will be Wasmer support for the likes of ESP32 MCUs? Thanks for any info.

Mmm, there is no link between RV64 support and ESP32 support. Also ESP32 is a ressource limited platform, so an interpreter approach might be more suited.

@syrusakbary syrusakbary modified the milestones: v3.0, v3.x Jun 29, 2022
@ptitSeb ptitSeb changed the base branch from master to feat_riscv_llvm October 20, 2022 06:35
@ptitSeb ptitSeb merged commit 73fa3f9 into wasmerio:feat_riscv_llvm Oct 20, 2022
@ptitSeb ptitSeb modified the milestones: v3.x, v3.1, v3.2 Nov 16, 2022
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4 participants