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RISC-V support #2800

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merged 5 commits into from
Oct 20, 2022
Merged

RISC-V support #2800

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b825880
Basic changes for RISC-V support
tnayuki Feb 16, 2022
5ff356d
RISC-V in compiler LLVM
tnayuki Feb 16, 2022
6bf4ea1
RISC-V support in dylib engine
tnayuki Feb 16, 2022
fe82b1f
RISC-V support in universal engine
tnayuki Feb 15, 2022
73fa3f9
Merge branch 'master' into risc-v
tnayuki Feb 20, 2022
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13 changes: 5 additions & 8 deletions Cargo.lock
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18 changes: 16 additions & 2 deletions Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -52,6 +52,7 @@ IS_LINUX := 0
IS_WINDOWS := 0
IS_AMD64 := 0
IS_AARCH64 := 0
IS_RISCV64 := 0

# Test Windows apart because it doesn't support `uname -s`.
ifeq ($(OS), Windows_NT)
Expand Down Expand Up @@ -80,6 +81,8 @@ else
IS_AMD64 := 1
else ifneq (, $(filter $(uname), aarch64 arm64))
IS_AARCH64 := 1
else ifneq (, $(filter $(uname), riscv64))
IS_RISCV64 := 1
else
# We use spaces instead of tabs to indent `$(error)`
# otherwise it's considered as a command outside a
Expand Down Expand Up @@ -114,8 +117,16 @@ compilers :=

# If the user didn't disable the Cranelift compiler…
ifneq ($(ENABLE_CRANELIFT), 0)
# … then it can always be enabled.
compilers += cranelift
# … then maybe the user forced to enable the Cranelift compiler.
ifeq ($(ENABLE_CRANELIFT), 1)
compilers += cranelift
# … otherwise, we try to check whether Cranelift works on this host.
else ifneq ($(IS_RISCV64), 1)
compilers += cranelift
endif
endif

ifneq (, $(findstring cranelift,$(compilers)))
ENABLE_CRANELIFT := 1
endif

Expand Down Expand Up @@ -241,6 +252,9 @@ ifeq ($(ENABLE_LLVM), 1)
else ifeq ($(IS_AARCH64), 1)
compilers_engines += llvm-universal
compilers_engines += llvm-dylib
else ifeq ($(IS_RISCV64), 1)
compilers_engines += llvm-universal
compilers_engines += llvm-dylib
endif
endif
endif
Expand Down
5 changes: 3 additions & 2 deletions lib/compiler-llvm/Cargo.toml
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Expand Up @@ -28,9 +28,10 @@ loupe = "0.1"

[dependencies.inkwell]
package = "inkwell"
version = "0.1.0-beta.4"
git = "https://github.com/TheDan64/inkwell.git"
rev = "a24642d"
default-features = false
features = ["llvm12-0", "target-x86", "target-aarch64"]
features = ["llvm12-0", "target-x86", "target-aarch64", "target-riscv"]

[build-dependencies]
cc = "1.0"
Expand Down
58 changes: 52 additions & 6 deletions lib/compiler-llvm/src/config.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -100,6 +100,13 @@ impl LLVM {
}

fn target_triple(&self, target: &Target) -> TargetTriple {
let architecture = if target.triple().architecture
== Architecture::Riscv64(target_lexicon::Riscv64Architecture::Riscv64gc)
{
target_lexicon::Architecture::Riscv64(target_lexicon::Riscv64Architecture::Riscv64)
} else {
target.triple().architecture
};
// Hack: we're using is_pic to determine whether this is a native
// build or not.
let operating_system = if target.triple().operating_system
Expand All @@ -125,7 +132,7 @@ impl LLVM {
target_lexicon::BinaryFormat::Elf
};
let triple = Triple {
architecture: target.triple().architecture,
architecture: architecture,
vendor: target.triple().vendor.clone(),
operating_system,
environment: target.triple().environment,
Expand Down Expand Up @@ -158,6 +165,14 @@ impl LLVM {
info: true,
machine_code: true,
}),
Architecture::Riscv64(_) => InkwellTarget::initialize_riscv(&InitializationConfig {
asm_parser: true,
asm_printer: true,
base: true,
disassembler: true,
info: true,
machine_code: true,
}),
// Architecture::Arm(_) => InkwellTarget::initialize_arm(&InitializationConfig {
// asm_parser: true,
// asm_printer: true,
Expand All @@ -179,16 +194,47 @@ impl LLVM {

let target_triple = self.target_triple(&target);
let llvm_target = InkwellTarget::from_triple(&target_triple).unwrap();
llvm_target
let llvm_target_machine = llvm_target
.create_target_machine(
&target_triple,
"generic",
&llvm_cpu_features,
match triple.architecture {
Architecture::Riscv64(_) => "generic-rv64",
_ => "generic",
},
match triple.architecture {
Architecture::Riscv64(_) => "+m,+a,+c,+d,+f",
_ => &llvm_cpu_features,
},
self.opt_level,
self.reloc_mode(),
self.code_model(),
match triple.architecture {
Architecture::Riscv64(_) => CodeModel::Medium,
_ => self.code_model(),
},
)
.unwrap()
.unwrap();

if let Architecture::Riscv64(_) = triple.architecture {
// TODO: totally non-portable way to change ABI
unsafe {
pub struct MyTargetMachine {
pub target_machine: *const u8,
}

let my_target_machine: MyTargetMachine = std::mem::transmute(llvm_target_machine);

*((my_target_machine.target_machine as *mut u8).offset(0x410) as *mut u64) = 5;
std::ptr::copy_nonoverlapping(
"lp64d\0".as_ptr(),
(my_target_machine.target_machine as *mut u8).offset(0x418),
6,
);

std::mem::transmute(my_target_machine)
}
Comment on lines +218 to +234
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This will need to be in llvm-sys or inkwell, right?

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Yes, but LLVM C API to change ABI doesn't seem to exist, so it should also be added.

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Thanks for the context.
Do you think we can create an issue on the LLVM project and add an extra comment in this source with a reference to the URL that new LLVM issue?

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Sorry for the late reply as I have been busy with my day job😢
I checked LLVM again, and I found that it seems by this change the correct ABI will be specified in LLVM 15, so I will try it.
llvm/llvm-project@4e115b7

} else {
llvm_target_machine
}
}
}

Expand Down
30 changes: 29 additions & 1 deletion lib/compiler-llvm/src/object_file.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -193,14 +193,29 @@ where
(object::Architecture::Aarch64, object::RelocationKind::PltRelative, 26) => {
RelocationKind::Arm64Call
}
(
object::Architecture::Riscv64,
object::RelocationKind::Elf(object::elf::R_RISCV_CALL_PLT),
0,
) => RelocationKind::RiscvCall,
(
object::Architecture::Riscv64,
object::RelocationKind::Elf(object::elf::R_RISCV_PCREL_HI20),
0,
) => RelocationKind::RiscvPCRelHi20,
(
object::Architecture::Riscv64,
object::RelocationKind::Elf(object::elf::R_RISCV_PCREL_LO12_I),
0,
) => RelocationKind::RiscvPCRelLo12I,
_ => {
return Err(CompileError::Codegen(format!(
"unknown relocation {:?}",
reloc
)));
}
};
let addend = reloc.addend();
let mut addend = reloc.addend();
let target = match reloc.target() {
object::read::RelocationTarget::Symbol(index) => {
let symbol = elf.symbol_by_index(index).map_err(map_object_err)?;
Expand Down Expand Up @@ -231,6 +246,19 @@ where
symbol_name_to_relocation_target(symbol_name)?
{
reloc_target
} else if let object::SymbolSection::Section(section_index) = symbol.section() {
// TODO: Encode symbol address into addend, I think this is a bit hacky.
addend = addend.wrapping_add(symbol.address() as i64);

if section_index == root_section_index {
root_section_reloc_target
} else {
if visited.insert(section_index) {
worklist.push(section_index);
}

elf_section_to_target(section_index)
}
} else {
return Err(CompileError::Codegen(format!(
"relocation targets unknown symbol {:?}",
Expand Down
19 changes: 14 additions & 5 deletions lib/compiler/src/relocation.rs
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Expand Up @@ -58,8 +58,12 @@ pub enum RelocationKind {
Arm64Movw2,
/// Arm64 movk/z part 3
Arm64Movw3,
// /// RISC-V call target
// RiscvCall,
/// RISC-V PC-relative high 20bit
RiscvPCRelHi20,
/// RISC-V PC-relative low 12bit, I-type
RiscvPCRelLo12I,
/// RISC-V call target
RiscvCall,
/// Elf x86_64 32 bit signed PC relative offset to two GOT entries for GD symbol.
ElfX86_64TlsGd,
// /// Mach-O x86_64 32 bit signed PC relative offset to a `__thread_vars` entry.
Expand All @@ -79,12 +83,14 @@ impl fmt::Display for RelocationKind {
Self::X86CallPCRel4 => write!(f, "CallPCRel4"),
Self::X86CallPLTRel4 => write!(f, "CallPLTRel4"),
Self::X86GOTPCRel4 => write!(f, "GOTPCRel4"),
Self::Arm32Call | Self::Arm64Call => write!(f, "Call"),
Self::Arm32Call | Self::Arm64Call | Self::RiscvCall => write!(f, "Call"),
Self::Arm64Movw0 => write!(f, "Arm64MovwG0"),
Self::Arm64Movw1 => write!(f, "Arm64MovwG1"),
Self::Arm64Movw2 => write!(f, "Arm64MovwG2"),
Self::Arm64Movw3 => write!(f, "Arm64MovwG3"),
Self::ElfX86_64TlsGd => write!(f, "ElfX86_64TlsGd"),
Self::RiscvPCRelHi20 => write!(f, "RiscvPCRelHi20"),
Self::RiscvPCRelLo12I => write!(f, "RiscvPCRelLo12I"),
// Self::MachOX86_64Tlv => write!(f, "MachOX86_64Tlv"),
}
}
Expand Down Expand Up @@ -137,7 +143,8 @@ impl Relocation {
| RelocationKind::Arm64Movw0
| RelocationKind::Arm64Movw1
| RelocationKind::Arm64Movw2
| RelocationKind::Arm64Movw3 => {
| RelocationKind::Arm64Movw3
| RelocationKind::RiscvPCRelLo12I => {
let reloc_address = start + self.offset as usize;
let reloc_addend = self.addend as isize;
let reloc_abs = target_func_address
Expand Down Expand Up @@ -171,7 +178,9 @@ impl Relocation {
.wrapping_add(reloc_addend as u32);
(reloc_address, reloc_delta_u32 as u64)
}
RelocationKind::Arm64Call => {
RelocationKind::Arm64Call
| RelocationKind::RiscvCall
| RelocationKind::RiscvPCRelHi20 => {
let reloc_address = start + self.offset as usize;
let reloc_addend = self.addend as isize;
let reloc_delta_u32 = target_func_address
Expand Down
41 changes: 41 additions & 0 deletions lib/engine-dylib/src/trampoline.rs
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Expand Up @@ -34,6 +34,13 @@ const AARCH64_TRAMPOLINE: [u8; 12] = [
// JMP [RIP + ...] FF 25 00 00 00 00
const X86_64_TRAMPOLINE: [u8; 6] = [0xff, 0x25, 0x00, 0x00, 0x00, 0x00];

// AUIPC t1, #... 17 03 00 00
// LD t1, #...(t1) 03 33 03 00
// JR t1 67 00 03 00
const RISCV64_TRAMPOLINE: [u8; 12] = [
0x17, 0x03, 0x00, 0x00, 0x03, 0x33, 0x03, 0x00, 0x67, 0x00, 0x03, 0x00,
];

fn emit_trampoline(
obj: &mut Object,
text: SectionId,
Expand Down Expand Up @@ -115,6 +122,40 @@ fn emit_trampoline(
)
.unwrap();
}
Architecture::Riscv64(_) => {
let (reloc1, reloc2) = match obj.format() {
BinaryFormat::Elf => (
RelocationKind::Elf(elf::R_RISCV_PCREL_HI20),
RelocationKind::Elf(elf::R_RISCV_PCREL_LO12_I),
),
_ => panic!("Unsupported binary format on Riscv64"),
};
let offset = obj.add_symbol_data(libcall_symbol, text, &RISCV64_TRAMPOLINE, 4);
obj.add_relocation(
text,
Relocation {
offset: offset,
size: 32,
kind: reloc1,
encoding: RelocationEncoding::Generic,
symbol: trampoline_table_symbols[libcall as usize],
addend: 0,
},
)
.unwrap();
obj.add_relocation(
text,
Relocation {
offset: offset + 4,
size: 32,
kind: reloc2,
encoding: RelocationEncoding::Generic,
symbol: libcall_symbol,
addend: 0,
},
)
.unwrap();
}
arch => panic!("Unsupported architecture: {}", arch),
};
}
Expand Down
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