Release v0.4.0 · intel/rohd

What's Changed

Fix #163 - invalid generated SystemVerilog for bit slicing on expressions by @mkorbel1 in #164
fix constant collapsing, fix #159 by @mkorbel1 in #160
Fix Combinational sensitivity detection - Issue #158 by @mkorbel1 in #166
Improve performance of Combinational execute by @mkorbel1 in #156
Rework script "run_coverage" by @chykon in #173
Use issue forms instead of old template by @chykon in #176
Upgrade lints package, make lints more strict, and fix new lint errors by @mkorbel1 in #174
[FIX-issue#99] Allowing negative logic index values by @RPG-coder-intc in #155
Remove accidental dontDeleteTmpFiles for a bus test by @mkorbel1 in #178
Improving GitHub Actions workflow and local testing by @chykon in #177
Fix badges in readme after workflow changes by @mkorbel1 in #179
Increase Dart SDK version by @chykon in #181
Fix #183, parsing of unsigned large binary integers by @mkorbel1 in #184
Update to contributor covenant v2.1 (fix #182) by @mkorbel1 in #185
Expose synthesis results from synth builder (fix #172) by @mkorbel1 in #186
Rename topModuleName to definitionName in ExternalSystemVerilogModule by @mkorbel1 in #187
Clean up names for ports by @mkorbel1 in #188
Add full SV reserved keyword list to sanitizer, fix #168 by @mkorbel1 in #189

Full Changelog: v0.3.2...v0.4.0